The present invention deals broadly with the field of electrical interconnect and testing systems for integrated circuits. More narrowly, however, the invention is related to an active wafer level contacting system for coupling an integrated circuit device positioned on a wafer with a tester intended to effect test analysis of the integrated circuit device. The preferred embodiment of the present invention includes an active wafer level contact system having at least a portion of the signal conditioning or integrated circuit test system located on the active wafer level contacting system.
In a typical semi-conductor production facility, each integrated circuit is tested using a tester apparatus. The tester apparatus may be connected to the integrated circuit through an interconnection system. The tester apparatus may test the functionality and performance of an integrated circuit through the interconnection system.
As modern semi-conductor devices increase in performance, for example speed, the manufacturer's ability to test these devices "at speed" has become increasingly more difficult. The testing of high performance semiconductor devices require precise impedance matching and minimal parasitic capacitance to limit distortion of the performance characteristics of the device under test.
Typically, integrated circuits are mass produced on a silicon wafer using integrated circuit wafer processing techniques. After the manufacturing of the integrated circuits is completed, each integrated circuit is removed from the silicon wafer for packaging. It has been proven to be highly cost effective and less time consuming to test the individual integrated circuits while they are still positioned on the wafer.
One prior art wafer level contacting device is a probe card contacting system. The probe card contacting system includes an opening which is larger than the integrated circuit device under test. Extending from the probe card through the opening are relatively rigid, fixed position metallic pins having sharpened points. The number of pins correspond to the number of input/output (I/O) pads on the semiconductor device. As the probe card is positioned over the integrated circuit device, the sharpened points on the metallic pins make direct contact with the corresponding I/O pads on the integrated circuit device under test, with the long cantilevered pins conducting electrical signals between the integrated circuit device under test and the probe card.
Coupled to the probe card is a tester for testing various performance characteristics of the integrated circuit device under test. The probe card may also include termination circuits, for example, resistors and capacitors, to condition the test signal output to the tester.
It is desirable to provide a wafer level contacting system for testing of high performance integrated circuit devices "at speed". The wafer level contacting system should provide signal conditioning, including precise impedance matching and minimal parasitic capacitances. Further, it is desirable to have an "active" wafer contacting system having active circuit devices integrated into the wafer level contacting system for a highly efficient, economical testing system.
It is to these dictates and shortcomings of the prior art that the present invention is directed. It is an active wafer level contacting system which addresses the dictates of the prior art and resolves problems thereof.